This invention relates to a semiconductor device and more particularly to a semiconductor device suited to a high integration and high speed semiconductor memory LSI.
As a previously known memory cell, there has been proposed, in Japanese Patent Unexamined Publication No. 53-43,485, a high speed bipolar memory cell having such a circuit construction as shown in FIG. 1. This memory cell is characterized in that diodes D.sub.1 and D.sub.2 are provided in parallel with load resistors R.sub.1 and R.sub.2, respectively and the parasitic capacitances of D.sub.1 and D.sub.2 are employed as capacitors C.sub.1 and C.sub.2. Moreover, a and b connect the cell with word lines W for accessing the memory cell, and S.sub.1 and S.sub.2 connect the cell with digit lines D and D for reading out the memory contents. Such an arrangement provides the advantages: (1) high speed switching is possible, (2) operation allowance is increased, and (3) a soft error rate due to .alpha. rays is low.
To realize these advantages, the capacitors C.sub.1 and C.sub.2 are required to have electrostatic capacitances of approximately 500 fF, respectively. To this end, as mentioned above, the electrostatic capacitances of Schottky barrier diodes D.sub.1 and D.sub.2, for example are employed in place of those of the capacitors. The Schottky diodes in that memory cell uses an interface of a platinum silicide (PtSi) layer and a silicon layer. Such a diode, however, only gives a capacitance up to about 3.4 fF/.mu.m.sup.2 so that it occupies an area as large as 150 .mu.m.sup.2, which is about 30% of the entire memory cell area, so as to provide the required electrostatic capacitance. Tis is a serious obstacle when manufacturing a high speed bipolar memory with a high integration.
In view of these circumstance, in Japanese Patent Unexamined Publication No. 59-171,157, for example, the memory cell has been reduced in its area by means of the techniques of (1) independently forming capacitors C.sub.1, C.sub.2 and Schottky diodes D.sub.1, D.sub.2, (2) using, as dielectrics of capacitors C.sub.1, C.sub.2, tantalum oxide with a higher relative permittivity, etc. However, there is still an eager demand for further reducing the area of the memory cell.